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MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
3ĆBit 4:1 MuxĆLatch
The MC10E/100E156 contains three 4:1 multiplexers followed by transparent latches with differential outputs. When both Latch Enables (LEN1, LEN2) are LOW, the latch is transparent, and output date is controlled by the multiplexer select controls (SEL0, SEL1). A logic HIGH on either LEN1 or LEN2 (or both) latches the outputs. The Master Reset (MR) overrides all other controls to set the Q outputs LOW.
• 950ps Max. D to Output • 850ps Max. LEN to Output • Differential Outputs • Asynchronous Master Reset • Dual Latch-Enables • Extended 100E VEE Range of – 4.2V to – 5.
MC100E156 Datasheet
