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MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
4-Bit ECL/TTL Load Reducing DRAM Driver
The MC10H/100H660 is a 4–bit ECL input, translating DRAM address driver, ideally suited for driving TTL compatible DRAM inputs from an ECL system. It is designed for use in high capacity, highly interleaved DRAM memory boards, that directly interface to a high speed, pipelined ECL bus interface, where new operations may be initiated to the board at up to a 50 MHz rate.
The latch provides the capability for the memory controller to propagate new addresses to different banks without having to wait for the address timing constraints to be satisfied from a previous memory operation.
MC100H660 Datasheet
