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MC14508B - Dual 4-Bit Latch

Features

  • MC 14508B MC 14508B 4.
  • LINE DATA BUS 4.
  • LINE DATA BUS 3.
  • STATE 4.
  • BIT LATCH 3.
  • STATE 4.
  • BIT LATCH DATA BUS MC14519B A B MC14508B 348.

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Full PDF Text Transcription

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MOTOROLA SEMICONDUCTOR TECHNICAL DATA Dual 4-Bit Latch The MC14508B dual 4–bit latch is constructed with MOS P–channel and N–channel enhancement mode devices in a single monolithic structure. The part consists of two identical, independent 4–bit latches with separate Strobe (ST) and Master Reset (MR) controls. Separate Disable inputs force the outputs to a high impedance state and allow the devices to be used in time sharing bus line applications. These complementary MOS latches find primary use in buffer storage, holding register, or general digital logic functions where low power dissipation and/or high noise immunity is desired. • 3–State Output • Supply Voltage Range = 3.
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