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MC145106 - PLL Frequency Synthesizer

General Description

P0 P8 Programmable Inputs (PDIP Pins 17 9; SOG Pins 19, 17 14, 12

9) Programmable divider inputs (binary).

Pin 2) Frequency input to programmable divider (derived from VCO).

Key Features

  • ansceivers. The VCO operates on frequency during transmit and is offset downward during receive. The offset corresponds to the receive IF (10.7 MHz) for channels having identical receive/transmit frequencies (simplex), and is (10.7.
  • 4.6 = 6.1) MHz for duplex channels. Carrier modulation is introduced in the loop during transmit. ÷ 29/210 OSC 10.24 MHz ÷2 MC145106.

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Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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MOTOROLA SEMICONDUCTOR TECHNICAL DATA Order this document by MC145106/D PLL Frequency Synthesizer CMOS The MC145106 is a phase–locked loop (PLL) frequency synthesizer constructed in CMOS on a single monolithic structure. This synthesizer finds applications in such areas as CB and FM transceivers. The device contains an oscillator/amplifier, a 210 or 211 divider chain for the oscillator signal, a programmable divider chain for the input signal, and a phase detector. The MC145106 has circuitry for a 10.24 MHz oscillator or may operate with an external signal. The circuit provides a 5.12 MHz output signal, which can be used for frequency tripling. A 29 programmable divider divides the input signal frequency for channel selection.