Datasheet Details
| Part number | MC145488 |
|---|---|
| Manufacturer | Motorola Semiconductor (now NXP Semiconductors) |
| File Size | 104.99 KB |
| Description | Dual Data Link Controller |
| Datasheet | MC145488_Motorola.pdf |
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Overview: MOTOROLA SEMICONDUCTOR TECHNICAL DATA Technical Summary Dual Data Link Controller This technical summary gives a brief overview of the MC145488 Dual Data Link Controller. The MC145488 is a two–channel ISDN LAPD controller with an on–chip direct memory access (DMA) controller. It is intended for ISDN terminal and switch applications where one or two channels of data will use HDLC–type protocols. The DDLC can also be used in local area, wide area network, and bridge router applications. Each serial interface can be clocked at data rates up to 10 Mbps. The DDLC can operate with microprocessors using clock frequencies up to 20.5 MHz. .. The DDLC is ideally suited for use with the MC145474 S/T–Transceiver. The interchip digital link (IDL) easily connects the chips together, providing a powerful layer one/layer two ISDN solution. A serial control port is provided to efficiently control the MC145474 or other ISDN family devices. The DDLC is patible with 68000 and 80186 bus structures.
| Part number | MC145488 |
|---|---|
| Manufacturer | Motorola Semiconductor (now NXP Semiconductors) |
| File Size | 104.99 KB |
| Description | Dual Data Link Controller |
| Datasheet | MC145488_Motorola.pdf |
|
|
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and electrical specifications.
It can be ordered from your local Motorola sales office or from the Motorola Literature Distribution Center as MC145488/D.
• Two Independent Full–Duplex Bit–Oriented Protocol Controllers Support HDLC, SDLC, CCITT X.25, CCITT Q.921 (LAPD), and V.120 at Basic and Primary Rates • Four–Channel On–Chip DMA Controller — 64 kbyte Address Range with Expansion Control — Internal Programmable Wait–State Generator — Two Buffer Descriptors for Each Receiver Channel • patible with 68000 and 80186 Bus Structures — Non–Multiplexed 16– or 8–Bit Data Bus — Frame Sizes up to 4096 bytes • Bit–Level HDLC Processing Including: — Flag Generation/Detection — Abort Generation/Detection — Zero Insertion/Deletion — CRC–CCITT Generation/Checking — Residue Bit Handler • TEI/SAPI Address parison — Three Address
| Part Number | Description |
|---|---|
| MC145480 | 5V PCM CODEC-FILTER |
| MC145481 | 3V PCM CODEC-FILTER |
| MC145482 | 5V 13-BIT LINEAR PCM CODEC-FILTER |
| MC145483 | 3V 13-BIT LINEAR PCM CODEC-FILTER |
| MC145484 | 5V PCM CODEC-FILTER |
| MC145402 | Serial 13-Bit Linear Codec |
| MC145403 | DRIVER/RECEIVERS |
| MC145404 | DRIVER/RECEIVERS |
| MC145405 | DRIVER/RECEIVERS |
| MC145406 | Driver / Receiver |