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MC14554B - 2-Bit by 2-Bit Parallel Binary Multiplier

Key Features

  • 49.
  • 5.08 0.39 0.50 1.27 BSC 1.40 1.65 2.54 BSC 0.21 0.38 3.18 4.31 7.62 BSC 0_ 15 _ 0.51 1.01.
  • B.
  • 1 8 C L.
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MOTOROLA SEMICONDUCTOR TECHNICAL DATA MC14554B 2-Bit by 2-Bit Parallel Binary Multiplier The MC14554B 2 x 2–bit parallel binary multiplier is constructed with complementary MOS (CMOS) enhancement mode devices. The multiplier can perform the multiplication of two binary numbers and simultaneously add two other binary numbers to the product. The MC14554B has two multiplicand inputs (X0 and X1), two multiplier inputs (Y0 and Y1), five cascading or adding inputs (K0, K1, M0, M1, and M2), and five sum and carry outputs (S0, S1, S2, C1 [S3], and C0). The basic multiplier can be expanded into a straightforward m–bit by n–bit parallel multiplier without additional logic elements.