Datasheet Summary
DUAL JK POSITIVE EDGE-TRIGGERED FLIP-FLOP
The MC54/74F109 consists of two high-speed, pletely independent transition clocked JK flip-flops. The clocking operation is independent of rise and fall times of the clock waveform. The JK design allows operation as a D flip-flop (refer to F74 data sheet) by connecting the J and K inputs together.
CONNECTION DIAGRAM
VCC CD2 J2 K2 CP2 SD2 Q2 Q2 16 15 14 13 12 11 10 9
CD J
K CP SD Q Q
CD1 J1 K1 CP1 SD1 Q1 Q1
12 CD1 J1
3456 K1 CP1 SD1 Q1
78 Q1 GND
FUNCTION TABLE (Each Half)
Input
Output
@ tn JK
@ tn + 1 QQ
No Change
Toggles
Asynchronous Inputs:
LOW Input to SD sets Q to HIGH level LOW Input to CD sets Q to...