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MC68HC705MC4 - Microcontrollers

General Description

3 VDD AND VSS 3 OSC1, OSC2 3 Crystal with Internal Components 4 Ceramic Resonator 4 External Clock 5 RESET 5 PA0, PA1/PWMA1, PA2/PWMB1, PA3/PWMA2, PA4/PWMB2, PA5/PWMA3, PA6/PWMB3, PA7 5 PB4/TDO, PB5/RDI, PB6, PB7 5 PC0:5/AD0:5, PC6/Vrefh, PC7/Vrefl 5 PD6/TCAP1/TCMP, PD7/TCAP2 5 IRQ (MASKABLE

Key Features

  • (all timing based on 3 MHz bus) 1 MASK.

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Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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HC705MC4GRS/D REV 1.5 68HC705MC4 SPECIFICATION (General Release) © January 17, 1995 CSIC System Design Group Austin, Texas The MC68HC705MC4 is an MCU device in a 28-pin DIP or SOIC package with the HC05 CPU core, a 16-bit timer including an output compare and two input captures, an 8-bit A/D converter with a 6 channel input multiplexer, a dual channel pulse width modulator (PWM), an SCI and a COP watchdog timer. The 4 K byte memory map has 3584 bytes of user ROM/EPROM and 176 bytes of RAM. Motorola reserves the right to make changes without further notice to any products herein to improve reliability, function or design.