MC68HC908KX2 Datasheet | Motorola Semiconductor

Description Label for pin 9 corrected in Figure 1-1 and Figure 1-2 $FF is the erase state of the FLASH, not $00. First bulleted paragraph under the subsection 16.5 Interrupts reworded for clarity April, 2001 0.1 Revision to the description of the CHx MAX bit and the note that follows that description Forced monitor mode information added to Table 18-1. In Figure 18-1, resistor value for connection between VTST and IRQ1 changed from 10 kΩ to 1 kΩ. 7.3 Features - Corrected third bullet 7.8.3 ICG Trim Register - Corrected description of the TRIM7:TRIM0 bits 15.3 Features - Corrected divide by factors in first bullet Figure 15-1. Timebase Block Diagram - Corrected divide-by-2 blocks Table 15-1. Timebase Divider Selection - Corrected last divider tap entry 1 Section 16. Timer Interface Module (TIM) - Timer discrepancies corrected throughout this section 20.5 Thermal Characteristics - Corrected SOIC thermal resistance and maximum junction temperature 20.6 5.0-Vdc DC Electrical Characteristics and 20.7 3.0-Vdc DC Electrical Characteristics - Corrected footnote for VDD supply current in stop mode Appendix B. MC68HC08KX8 Overview - Added to supply exception information for the MC68HC08KX8 Page Number(s) 32, 33 82, 252, 255 233 242 257 258 101 134 216 217 218 223 281 A G R E E M E N T February, 2002 - D I S C L O S U R E 282 and 283 Technical Data 4 MC68HC908KX8 - MC68HC908KX2 - MC68HC08KX8 - Rev. 1.0 MOTOROLA Technical Data - MC68HC908KX8 - MC68HC908KX2 - MC68HC08KX8 List of Sections Section 1. General Description - - - - 29 Section 2. Memory Map - - - - - . 37 Section 3. Random-Access Memory (RAM) - - 47 Section 4. FLASH Memory - - - - . . . . 49 Section 5. Central Processor Unit (CPU) - - . . 59 Section 6. System Integration Module (SIM) - . . . . 77 Section 7. Internal Clock Generator Module (ICG)....