MC74HC125A Datasheet | Motorola Semiconductor

MOTOROLA SEMICONDUCTOR TECHNICAL DATA Quad 3-State Noninverting Buffers High- Performance Silicon- Gate CMOS The MC74HC125A and MC74HC126A are identical in pinout to the LS125 and LS126. The device inputs are patible with standard CMOS outputs; with pullup resistors, they are patible with LSTTL outputs. The HC125A and HC126A noninverting buffers are designed to be used with 3- state memory address drivers, clock drivers, and other bus- oriented systems. The devices have four separate output enables that are active- low (HC125A) or active- high (HC126A). - Output Drive Capability: 15 LSTTL Loads - Outputs Directly Interface to CMOS, NMOS, and TTL - Operating Voltage Range: 2.0 to 6.0 V - Low Input Current: 1.0 µA - High Noise Immunity Characteristic of CMOS Devices - In pliance with the Requirements Defined by JEDEC Standard No. 7A - Chip plexity: 72 FETs or 18 Equivalent Gates LOGIC DIAGRAM HC125A Active- Low Output Enables HC126A Active- High Output Enables A1 OE1 5 A2 OE2 9 A3 OE3 12 A4 13 OE4 3 Y1 A1 OE1 Y2 A2 OE2...