MC74VHCT373A Datasheet | Motorola Semiconductor

MOTOROLA SEMICONDUCTOR TECHNICAL DATA Octal D-Type Latch with 3-State Output The MC74VHCT373A is an advanced high speed CMOS octal latch with 3- state output fabricated with silicon gate CMOS technology. It achieves high speed operation similar to equivalent Bipolar Schottky TTL while maintaining CMOS low power dissipation. This 8- bit D- type latch is controlled by a latch enable input and an output enable input. When the output enable input is high, the eight outputs are in a high impedance state. The internal circuit is posed of three stages, including a buffer output which provides high noise immunity and stable output. The VHCT inputs are patible with TTL levels. This device can be used as a level converter for interfacing 3.3V to 5.0V, because it has full 5V CMOS level output swings. The VHCT373A input and output (when disabled) structures provide protection when voltages between 0V and 5.5V are applied, regardless of the supply voltage. These input and output structures help prevent device destruction caused by supply voltage - input/output voltage mismatch, battery backup, hot insertion, etc. - - - - - - - - - - - High Speed: t PD = 7.7ns (Typ) at VCC = 5V Low Power Dissipation: ICC = 4µA (Max) at TA = 25°C TTL- patible Inputs: VIL = 0.8V; VIH = 2.0V Power Down Protection Provided on Inputs and Outputs Balanced Propagation Delays Designed for 4.5V to 5.5V Operating Range Low Noise: VOLP = 1.6V (Max) Pin and Function patible with Other Standard Logic Families Latchup Performance Exceeds 300m A ESD Performance: HBM > 2000V; Machine Model > 200V Chip plexity: 196 FETs or 49 Equivalent Gates DW SUFFIX 20- LEAD SOIC PACKAGE CASE 751D- 04 DT SUFFIX 20- LEAD TSSOP PACKAGE CASE 948E- 02 M SUFFIX 20- LEAD SOIC EIAJ PACKAGE CASE 967- 01 ORDERING INFORMATION MC74VHCTXXXADW SOIC MC74VHCTXXXADT TSSOP MC74VHCTXXXAM SOIC EIAJ PIN ASSIGNMENT LOGIC DIAGRAM 3 D0 4 D1 7 D2 8 D3 13 D4 14 D5 17 D6 18 D7 LE OE 11 1 2 5 6 9 12 15 16 19 Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 OE Q0 D0 D1...