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MC88LV915 - LOW SKEW CMOS PLL CLOCK DRIVER

General Description

on page 11).

Q4, Q5 and Q/2 into a high impedance state (3

state).

Q4, Q5 and Q/2 will be reset in the low state, with 2X_Q being the inverse of the selected SYNC input.

Key Features

  • Five Outputs (Q0.
  • Q4) with Output.
  • Output Skew < 500 ps each being phase and frequency locked to the SYNC input.
  • The phase variation from part.
  • to.
  • part between the SYNC and.

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Full PDF Text Transcription (Reference)

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MOTOROLA SEMICONDUCTOR TECHNICAL DATA Low Voltage Low Skew CMOS PLL Clock Driver, 3-State The MC88LV915T Clock Driver utilizes phase–locked loop technology to lock its low skew outputs’ frequency and phase onto an input reference clock. It is designed to provide clock distribution for high performance PC’s and workstations. The PLL allows the high current, low skew outputs to lock onto a single clock input and distribute it with essentially zero delay to multiple components on a board. The PLL also allows the MC88LV915T to multiply a low frequency input clock and distribute it locally at a higher (2X) system frequency.