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MC88LV926DW - LOW SKEW CMOS PLL 68060 CLOCK DRIVER

General Description

of the RST_IN/RST_OUT(LOCK) Functionality The RST_IN and RST_OUT(LOCK) pins provide a 68030/040/060 processor reset function, with the RST_OUT pin also acting as a lock indicator.

up, the RST_OUT pin will be in the low state until steady sta

Key Features

  • 3.3V ± 0.3V or 5.0V ±5%) Symbol tRISE/FALL1 All Outputs tRISE/FALL1 2X_Q Output tpulse width(a)1 (Q0, Q1, Q2, Q3) tpulse width(b)1 (2X_Q Output) tSKEWr1,2 (Rising) Parameter Rise/Fall Time, into 50Ω Load Rise/Fall Time into a 50Ω Load Output Pulse Width Q0, Q1, Q2, Q3 at 1.65V.

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MC88LV926 LOW SKEW CMOS PLL 68060 CLOCK DRIVER
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Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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MOTOROLA SEMICONDUCTOR TECHNICAL DATA Low Skew CMOS PLL 68060 Clock Driver The MC88LV926 Clock Driver utilizes phase–locked loop technology to lock its low skew outputs’ frequency and phase onto an input reference clock. It is designed to provide clock distribution for CISC microprocessor or single processor RISC systems. The RST_IN/RST_OUT(LOCK) pins provide a processor reset function designed specifically for the MC68/EC/LC030/040/060 microprocessor family. To support the 68060 processor, the 88LV926 operates from a 3.3V as well as a 5.0V supply. The PLL allows the high current, low skew outputs to lock onto a single clock input and distribute it with essentially zero delay to multiple locations on a board.