Datasheet Details
| Part number | MC92300 |
|---|---|
| Manufacturer | Motorola Semiconductor (now NXP Semiconductors) |
| File Size | 42.20 KB |
| Description | VITERBI Decoder for Digital TV |
| Datasheet | MC92300_MotorolaInc.pdf |
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Overview: MOTOROLA SEMICONDUCTOR TECHNICAL DATA Current Information@.mot./ADC MC92300 Product Preview VITERBI Decoder for Digital TV DTVVIT This product preview describes a high performance device, a Viterbi Decoder, for Digital-TV applications according to the EBU defined DVB transmission standard for satellite and cable Set-Top systems. RESET_N BITCLK VO VLCK VFF VEF SR[2:0] VC0,VC1[2:0] VDCLK SYMCLK VTSTI[1:0] Viterbi Decoder - Capability Specification • • • • • • • Operates at max. 50MBits/s output rate to work with all present DVB channels Implements K=7, (1718,1338) Viterbi decoder for rates 1/2, 2/3, 3/4, 5/6 and 7/8 with a survivor depth of 96 Code rate and synchronization control programmable via I2C standard serial bus Automatic rate selection and signal quality output (qval) Full/empty flag generation of input FIFO for system monitoring of VDCLK/BITCLK ratio Simplified system design with internal PLL for the generation of output BITCLK from the ining VDCLK for all depuncturing modes Available in a 128QFP package SDA DSA[6:0] SCL Ordering Information Device MC92300CG Package 128QFP VFF VC1[2:0] VC2[2:0] VDCLK VEF Synchronizer FIFO Depuncturing Viterbi Core VO APLL SYMCLK VLCK SR QVAL 2 VTSTI[1:0] BITCLK I2C Interface 7 SCL DSA SDA RESET_N Figure 1. Viterbi Decoder Block Diagram This document contains information on a new product. Specifications and information herein are subject to change without notice. © MOTOROLA, INC.
| Part number | MC92300 |
|---|---|
| Manufacturer | Motorola Semiconductor (now NXP Semiconductors) |
| File Size | 42.20 KB |
| Description | VITERBI Decoder for Digital TV |
| Datasheet | MC92300_MotorolaInc.pdf |
|
|
|
The Viterbi Decoder contains the Viterbi core logic, which operates the K=7 convolutional code and generates a lock indication after successful acquisition.
The core works with the main clock BITCLK, which provides the output data VO (output of the Viterbi).
This clock is generated by the integrated bit clock generator circuit and is adjusted according to the programmed depuncturing rate.
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