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MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Order this document by MCM62110/D
32K x 9 Bit Synchronous Dual I/O or Separate I/O Fast Static RAM with Parity Checker
The MCM62110 is a 294,912 bit synchronous static random access memory organized as 32,768 words of 9 bits, fabricated using Motorola’s high–performance silicon–gate CMOS technology. The device integrates a 32K x 9 SRAM core with advanced peripheral circuitry consisting of address registers, two sets of input data registers, two sets of output latches, active high and active low chip enables, and a parity checker. The RAM checks odd parity during RAM read cycles. The data parity error (DPE) output is an open drain type output which indicates the result of this check.
MCM62110 Datasheet
