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MCM6229BB - 256K x 4 Bit Static Random Access Memory

Key Features

  • urs during the overlap of E low and W low. 2. Product sensitivities to noise require proper grounding and decoupling of power supplies as well as minimization or elimination of bus contention conditions during read and write cycles. 3. If G goes low coincident with or after W goes low, the output will remain in a high.
  • impedance state. 4. All timings are referenced from the last valid address to the first transitioning address. 5. Transition is measured ± 500 mV from steady.
  • state.

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Other Datasheets by Motorola Semiconductor (now NXP Semiconductors)

Part Number Description
MCM6229B 256K x 4 Bit Static Random Access Memory
MCM6226A 128K x 8 Bit Static Random Access Memory
MCM6226B 128K x 8 Bit Static Random Access Memory
MCM6226BB 128K x 8 Bit Static Random Access Memory
MCM6227A 1M x 1 Bit Static Random Access Memory

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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MOTOROLA SEMICONDUCTOR TECHNICAL DATA Order this document by MCM6229BB/D Product Preview MCM6229BB XJ PACKAGE 400 MIL SOJ CASE 810–03 256K x 4 Bit Static Random Access Memory The MCM6229BB is a 1,048,576 bit static random access memory organized as 262,144 words of 4 bits. Static design eliminates the need for external clocks or timing strobes while CMOS circuitry reduces power consumption and provides for greater reliability. The MCM6229BB is equipped with both chip enable (E) and output enable (G) pins, allowing for greater system flexibility and eliminating bus contention problems. The MCM6229BB is available in 300 mil and 400 mil, 28 lead surface–mount SOJ packages.