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MCM67D709 - 128K x 9 Bit Synchronous Dual I/O Fast Static RAM

Key Features

  • 7.5.
  • Unit ns ns ns ns ns ns ns 3, 4 3 Notes 1, 2 Hold Times:.
  • ns Output Enable High to Q High.
  • Z Output Hold from Output Enable High Output Enable Low to Q Active Output Enable Low to Output Valid 6.
  • 5 8.
  • 6 ns ns ns ns 4 4 4 NOTES: 1. A read is defined by W high for the setup and hold times. 2. All read cycle timing is referenced from K, SOE, or POE. 3. K.

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Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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MOTOROLA SEMICONDUCTOR TECHNICAL DATA Order this document by MCM67D709/D 128K x 9 Bit Synchronous Dual I/O Fast Static RAM The MCM67D709 is a 1,179,648 bit synchronous static random access memory organized as 131,072 words of 9 bits, fabricated using Motorola’s high–performance silicon–gate BiCMOS technology. The device integrates a 128K x 9 SRAM core with advanced peripheral circuitry consisting of address registers, two sets of input data registers and two sets of output latches. This device has increased output drive capability supported by multiple power pins. Asynchronous inputs include the processor output enable (POE) and the system output enable (SOE). The address inputs (A0 – A16) are synchronous and are registered on the falling edge of clock (K).