Datasheet4U Logo Datasheet4U.com

MCM67Q909 - 512K x 9 Bit Separate I/O Synchronous Fast Static RAM

Key Features

  • separate TTL input and output buffers, which drive 3.3 V output levels, and incorporates input and output registers on.
  • board with high speed SRAM. It also features transparent.
  • write and data pass.
  • through capabilities. The synchronous design allows for precise cycle control with the use of an external single clock (K). The addresses (A0.
  • A18), data input (D0.
  • D8), data output (Q0.
  • Q8), write.
  • enable (W), chip.
  • enable (E), and output.

📥 Download Datasheet

📁 Similar Datasheet

Part Number Description Manufacturer
MCM6705A 32K x 9 Bit Static RAM Motorola Semiconductor
MCM6064 8K x 8-Bit CMOS SRAM Motorola Semiconductor
MCM60L64 8K x 8-Bit CMOS SRAM Motorola Semiconductor
MCM6229A 256K x 4-Bit Static RAM Motorola Semiconductor
MCM6306D 32K x 8-Bit 3.3V Fast Static RAM Motorola Semiconductor

Other Datasheets by Motorola Semiconductor (now NXP Semiconductors)

Part Number Description
MCM67Q709 128K x 9 Bit Separate I/O Synchronous Fast Static RAM
MCM67Q709A 128K x 9 Bit Separate I/O Synchronous Fast Static RAM
MCM67Q804 256K x 4 Bit Separate I/O Synchronous Fast Static RAM
MCM6706A 32K x 8 Bit Static Random Access Memory
MCM6706AR 32K x 8 Bit Static Random Access Memory

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
MOTOROLA SEMICONDUCTOR TECHNICAL DATA Order this document by MCM67Q909/D Advance Information MCM67Q909 512K x 9 Bit Separate I/O Synchronous Fast Static RAM The MCM67Q909 is a 4M–bit static random access memory, organized as 512K words of 9 bits. It features separate TTL input and output buffers, which drive 3.3 V output levels, and incorporates input and output registers on–board with high speed SRAM. It also features transparent–write and data pass–through capabilities. The synchronous design allows for precise cycle control with the use of an external single clock (K). The addresses (A0 – A18), data input (D0 – D8), data output (Q0 – Q8), write–enable (W), chip–enable (E), and output–enable (G), are registered on the rising edge of clock (K).