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MCM72BF64 - 256KB and 512KB BurstRAM Secondary Cache

Download the MCM72BF64 datasheet PDF. This datasheet also covers the MCM72BF32 variant, as both devices belong to the same 256kb and 512kb burstram secondary cache family and are provided as variant models within a single manufacturer datasheet.

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Note: The manufacturer provides a single datasheet file (MCM72BF32_MotorolaInc.pdf) that lists specifications for multiple related part numbers.

Other Datasheets by Motorola Semiconductor (now NXP Semiconductors)

Part Number Description
MCM72BF32 256KB and 512KB BurstRAM Secondary Cache
MCM72BA32 256KB and 512KB BurstRAM Secondary Cache
MCM72BA64 256KB and 512KB BurstRAM Secondary Cache
MCM72BB32 256KB and 512KB BurstRAM Secondary Cache
MCM72BB64 256KB and 512KB BurstRAM Secondary Cache
MCM72CB32 256KB and 512KB BurstRAM Secondary Cache Module
MCM72CB64 256KB and 512KB BurstRAM Secondary Cache Module
MCM72CF32 256KB and 512KB BurstRAM Secondary Cache Module
MCM72CF64 256KB and 512KB BurstRAM Secondary Cache Module
MCM72F10 8MB Synchronous Fast Static RAM Module

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
MOTOROLA SEMICONDUCTOR TECHNICAL DATA 256KB and 512KB BurstRAM™ Secondary Cache Module for Pentium™ The MCM72BF32SG and MCM72BF64SG are designed to provide a burstable, high performance, 256K/512K L2 cache for the Pentium microprocessor. The modules are configured as 32K x 72 and 64K x 72 bits in a 160 pin card edge memory module. Each module uses four of Motorola’s MCM67B518 or MCM67B618 BiCMOS BurstRAMs. All 72 I/Os are series terminated for added noise immunity. Bursts can be initiated with either address status processor (ADSP) or address status controller (ADSC). Subsequent burst addresses are generated internal to the BurstRAM by the burst advance (ADV) input pin. Write cycles are internally self timed and are initiated by the rising edge of the clock (K) input.