MPC5200ID Datasheet | Motorola Semiconductor

Overview 1 Features 1 Electrical and Thermal Characteristics 5 Package Description 60 System Design Information 69 Ordering Information 74 Document Revision History 75 The information in this document is subject to change. For the latest data on the MPC5200, visit .mobilegt. and proceed to the MPC5200 Product Summary Page. Overview The MPC5200 integrates a high performance MPC603e series G2_LE core with a rich set of peripheral functions focused on munications and systems integration. The G2_LE core design is based on the Power PC® core architecture. MPC5200 incorporates an innovative Bestm I/O subsystem, which isolates routine maintenance of peripheral functions from the embedded G2_LE core. The MPC5200 contains a SDRAM/DDR Memory Controller, a flexible External Bus Interface, PCI Controller, USB, ATA, Ethernet, six Programmable Serial Controllers (PSC), I2C, SPI, CAN, J1850, Timers, and GPIOs. - Features MPC603e series G2_LE core - - - - - - - - - - - - - Superscalar architecture 760 MIPS at 400 MHz (-40 to +85 o C) 16 k Instruction cache, 16 k Data cache Double precision FPU Instruction and Data MMU Standard and Critical interrupt capability up to 132-MHz operation SDRAM and DDR SDRAM support 256-MByte addressing range per CS, two CS available 32-bit data bus Built-in initialization and refresh Key features are shown below. SDRAM / DDR Memory Interface Flexible multi-function External Bus Interface - Supports interfacing to ROM/Flash/SRAM memories or other memory mapped devices For More Information On This Product, Go to: .freescale. Freescale Semiconductor, Inc. Features - - - - - - - - - - - 8 programmable Chip Selects Non multiplexed data access using 8/16/32 bit databus with up to 26-bit address Short or Long Burst capable Multiplexed data access using 8/16/32 bit databus with up to 25-bit...