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MPC952 - LOW VOLTAGE PLL CLOCK DRIVER

General Description

PLL Power Supply Output Buffer Power Supply Internal Core Logic Power Supply Internal Ground Output Buffer Ground Control Pin VCO_Sel MR/OE 12 11 10 PLL_En Logic ‘0’ fVCO Output Enable Enable PLL Logic ‘1’ fVCO/2 High Z Disable PLL fsela 0 1 Qan ÷4 ÷6 fselb 0 1 Qbn ÷4 ÷2 fselc 0 1 Qcn ÷2 ÷4 MPC952

Key Features

  • a fully integrated PLL with no external components required. With output frequencies of up to 180MHz and eleven low skew outputs the MPC952 is well suited for high performance designs. The device employs a fully differential PLL design to optimize jitter and noise rejection performance. Jitter is an increasingly important parameter as more microprocessors and ASiC’s are employing on chip PLL clock distribution. www. DataSheet4U. com MPC952 LOW.

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Other Datasheets by Motorola Semiconductor (now NXP Semiconductors)

Part Number Description
MPC950 (MPC950 / MPC951) LOW VOLTAGE PLL CLOCK DRIVER
MPC951 (MPC950 / MPC951) LOW VOLTAGE PLL CLOCK DRIVER
MPC953 LOW VOLTAGE PLL CLOCK DRIVER
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MPC9100 DUAL PLL CLOCK GENERATOR

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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MOTOROLA SEMICONDUCTOR TECHNICAL DATA Low Voltage PLL Clock Driver The MPC952 is a 3.3V compatible, PLL based clock driver device targeted for high performance clock tree applications. The device features a fully integrated PLL with no external components required. With output frequencies of up to 180MHz and eleven low skew outputs the MPC952 is well suited for high performance designs. The device employs a fully differential PLL design to optimize jitter and noise rejection performance. Jitter is an increasingly important parameter as more microprocessors and ASiC’s are employing on chip PLL clock distribution. www.DataSheet4U.