DESCRIPTION
The SN54/74LS168 and SN54/74LS169 use edgetriggered D-type flip-flops that have no constraints on changing the control or data input signals in either state of the Clock. The only requirement is that the various inputs attain the desired state at least a set-up time before the rising edge of the clock and remain valid for the recommended hold time thereafter. The parallel load operation takes precedence over the other operations, as indicated in the Mode Select Table. When PE is LOW, the data on the P0 – P3 inputs enters the flip-flops on the next rising edge of the Clock. In orde
Motorola
