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SN54LS193 - PRESETTABLE 4-BIT BINARY UP/DOWN COUNTER

Download the SN54LS193 datasheet PDF. This datasheet also covers the SN54LS193J variant, as both devices belong to the same presettable 4-bit binary up/down counter family and are provided as variant models within a single manufacturer datasheet.

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Note: The manufacturer provides a single datasheet file (SN54LS193J_MotorolaInc.pdf) that lists specifications for multiple related part numbers.

📁 Similar Datasheet

Part Number Description Manufacturer
SN54LS193 SYNCHRONOUS 4-BIT UP/DOWN COUNTERS Texas Instruments
SN54LS190 PRESETTABLE BCD/DECADE UP/DOWN COUNTER Motorola Inc
SN54LS190 SYNCHRONOUS UP/DOWN COUNTERS Texas Instruments
SN54LS191 SYNCHRONOUS UP/DOWN COUNTERS Texas Instruments
SN54LS192 PRESETTABLE BCD/DECADE UP/DOWN COUNTER Motorola Inc

Other Datasheets by Motorola Semiconductor (now NXP Semiconductors)

Part Number Description
SN54LS191 PRESETTABLE BCD/DECADE UP/DOWN COUNTER
SN54LS197 4-STAGE PRESETTABLE RIPPLE COUNTERS
SN54LS136 QUAD 2-INPUT EXCLUSIVE OR GATE
SN54LS14 SCHMITT TRIGGERS DUAL GATE/HEX INVERTER
SN54LS148 10-LINE-TO-4-LINE AND 8-LINE-TO-3-LINE PRIORITY ENCODERS

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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PRESETTABLE BCD/DECADE UP/DOWN COUNTER PRESETTABLE 4-BIT BINARY UP/DOWN COUNTER The SN54/74LS192 is an UP/DOWN BCD Decade (8421) Counter and the SN54/74LS193 is an UP/DOWN MODULO-16 Binary Counter. Separate Count Up and Count Down Clocks are used and in either counting mode the circuits operate synchronously. The outputs change state synchronous with the LOW-to-HIGH transitions on the clock inputs. Separate Terminal Count Up and Terminal Count Down outputs are provided which are used as the clocks for a subsequent stages without extra logic, thus simplifying multistage counter designs. Individual preset inputs allow the circuits to be used as programmable counters. Both the Parallel Load (PL) and the Master Reset (MR) inputs asynchronously override the clocks. • Low Power . . .