Overview: !Note •PPleleaasseerreeaaddrraatitninggaanndd!!CCAAUUTTIOIONN((foforrsstotorraaggee,,ooppeerraatitningg,,rraatitningg,,ssooldldeerriningg,,mmoouunntitninggaannddhhaannddlilningg))ininththisisPcDatFalcoagtatolopgrteovepnretvsemnot ksimngokaindg/oarndb/uorrnbinugr,neintgc., etc. N91E7.pdf 03.5.13 •TThhisisccaatatalologghhaassoonnlylytytyppiciacal sl pspeecicficfiactaiotinosn.sTbheecraeufosree,thyeorueaisrenroeqsupeascteedfotrodaeptapirloevdesopuercpifircoadtuiocnt ss.pTehceifirceafotioren,spoleratosetranpsparocvt ethoeuarppprroodvuacl tsshpeeectifoicraptiroondsucotrstrpaencsifaiccatitohnesabpepfororevaolrsdheerientgf.or product specifications before ordering. Chip Multilayer Delay Lines
Chip Multilayer Delay Lines 1 3.2±0.2 1.1±0.2 1.60±0.2 0.25+0.1/-0.15 0.5±0.1 This Delay Line was developed by applying ceramic (3) (2) (1) multilayering and hole technology. It consists of copper line and low dielectric constant material and incorporates metal shields. LDH series are very small (4) (8)
(5) (6) (7) 0.25+0.1/-0.15 and made for use at high frequencies. 0.35±0.2 0.45±0.