MUAC8K64 Datasheet | Music Semiconductors

mily consists of 4K and 8K x 64-bit Routing Co Processors (RCPs) with a 32-bit wide data interface and a 32-bit ternary pare instruction. The device is designed for use in layer 3 switches, routers, and layer 2 switches to provide very high throughput address translation using tables held in external RAM. The MUAC RCP has a fully deterministic search time, independent of the size of the list and the position of the data in the list. This unique feature guarantees that the wire speed address recognition does not impact the latency or induce some jitter on the latency of the global system. Address fields from the packet header are pared against a list of entries stored in the array. As a result of the parison, the MUAC RCP generates an index that is used to access an external RAM where port mapping data and other associated information is stored. A set of control states provides a powerful and flexible control interface to the MUAC RCP. This control structure allows memory read and write, register read and write, data move, parison, validity control, addressing control, and...