FEATURES
l l l l l l l l l l l l l l 8051 core. 384-bytes internal RAM. 32K-bytes program Flash ROM. 14-channels 5V open-drain PWM DAC, 10 dedicated channels and 4 channels shared with I/O pin. 28 bi-direction I/O pin,12 dedicated pin,12 shared with DAC, 4 shared with DDC/IIC interface. 3-output pin shared with H/V sync output and self test output pins. SYNC processor for composite separation, polarity and frequency check, and polarity adjustment. Built-in monitor self-test pattern generator. Built-in low power reset circuit. One slave mode IIC interface and one master mode IIC interface. IIC interface for DDC1/DDC2B and EEPROM, only one EEPROM needed to store DDC1/DDC2B and display mode information. Dual 4-bit ADC or 4 channel 6-bit ADC. Watchdog timer with programmable interval. 40-pin PDIP and 44-pin PLCC package. GENERAL DESCRIPTION
BLOCK DIAGRAM STOUT P1.0-7 X1 P0.0-7 RD WR P0.0-7 RD WR XFR HSYNC H / VSYNC CONTROL VSYNC HBLANK VBLANK X2 8051 CORE INT 1 RST WATCH-DOG TIMER RST P2.0...