NT5SV8M8DT Description
These synchronous devices achieve high-speed data transfer rates of up to 200MHz by employing a pipeline chip architecture that synchronizes the output data to a system clock. The chip is fabricated with NTC’ s advanced 64Mbit single transistor CMOS DRAM process technology. The device is designed to ply with all JEDEC standards set for synchronous DRAM products, both electrically and mechanically.
NT5SV8M8DT Key Features
- High Performance
- 5.4 -7 143 7 CL=3
- 5.4 Units MHz ns CKs ns ns
- 5.4 --5.4
- Single Pulsed RAS Interface
- Fully Synchronous to Positive Clock Edge
- Four Banks controlled by BS0/BS1 (Bank Select)