UPD23C64202L Description
The µPD23C64202L is a 67,108,864 bits synchronous mask-programmable ROM with multiplexed address bus. The word organization is selectable (WORD mode : 4,194,304 words by 16 bits, DOUBLE WORD mode.
UPD23C64202L Key Features
- Fully synchronous mask-ROM; all signals referenced to a positive clock edge
- Word organization : 4,194,304 words by 16 bits (WORD mode) 2,097,152 words by 32 bits (DOUBLE WORD mode)
- Operation frequency : up to 100 MHz
- Programmable wrap type : Sequential or Interleave
- Programmable burst length : 4, 8
- Programmable /CAS latency : 3, 4, 5 or 6
- Programmable /RAS latency : 1, 2
- Burst termination by BURST STOP mand
- LVTTL patible inputs and outputs