UPD65948S1
Overview
w w at .D w aS e e h U 4 t m o .c VRC4375 System Controller August 2000 The VRC4375TM system controller is a software-configurable chip that interfaces directly with an NEC VR43xxTM 64-bit MIPS RISC CPU and PCI bus without external logic or buffering. The system controller also interfaces with memory (SDRAM, EDO, fast-page DRAM, and flash/boot ROM) with minimal to no buffering.
- Direct connection to the 66 MHz VR43xx CPU bus 3.3-volt I/O Support for all VR43xx bus cycles Little-endian or big-endian byte ordering modes Y Memory Interface * * * * * * * * * * * * * * * *
- w w .D w Support for boot ROM/flash memory, base memory, and up to two SIMMs SIMM capacity of up to 128 MB Programmable address ranges for base and SIMM memory Support for two-bank 4/16 Mb devices and four-bank 64/128/256 Mb devices CAS latency of 2 or 3 in base memory or SIMM SDRAM, programmable to support faster new devices or slower legacy devices SIMM burst access time programmable in one or two cycle(s) 66 MHz memory bus 64 MB base memory range: SDRAM and EDO DRAM 256 MB SIMM memory range: SDRAM, EDO and fast-page DRAM Several speed grades supported within each memory range Open DRAM page maintained within base memory Eight-word (32-byte) write FIFO (CPU to memory) Two-word (8-byte) prefetch FIFO (memory to CPU or memory to PCI) On-chip DRAM and SDRAM refresh generation Up to 64 MB of write-protectable boot ROM or up to 64 MB of flash ROM Flash/boot ROM devices with 8-/16-/32-bit configuration support Programmable timing to inter
