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D720133 - UPD720133

General Description

2.2 Pin Setting Settings of the SCL, SDA and unused pins (TEST and SCAN) are recommended as follows.

Please note that the setting of the SCL depends on size of Serial ROM.

Table 2-2.

Key Features

  • Compliant with Universal Serial Bus Specification Revision 2.0 (Data Rate 12/480 Mbps).
  • Compliant with ATA/ATAPI-6 (LBA48, PIO Mode 0-4, Multi Word DMA Mode 0-2, Ultra DMA Mode 0-4).
  • USB2.0 high-speed bus powered device capability.
  • Certified by USB implementers forum and granted with USB 2.0 high-speed Logo (TID: 40001985).
  • One USB2.0 high-speed transceiver / receiver with full-speed transceiver / receiver.
  • USB2.0 High-speed or Full-speed pa.

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Other Datasheets by NEC (now Renesas Electronics)

Part Number Description
D720100AGM UPD720100AGM
D720101 UPD720101
D720112GK UPD720112
D72001C UPD72001C
D720200 UPD720200

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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PRELIMINARY DATA SHEET MOS INTEGRATED CIRCUIT µPD720133 USB2.0 to IDE Bridge The µPD720133 is designed to function as a bridge between USB 2.0 and ATA/ATAPI. The µPD720133 complies with the Universal Serial Bus Specification Revision 2.0 full-/high-speed signaling and works up to 480 Mbps. The µPD720133 consists of a CISC processor, an ATA/ATAPI controller, an endpoint controller (EPC), a serial interface engine (SIE), and an USB2.0 transceiver. The USB2.0 protocol and class specific protocols (bulk only protocol) are handled by the USB2.0 transceiver, the SIE and the EPC. The V30MZ CISC processor in the µPD720133 takes care of the activities in the transport layer. The firmware controlling the µPD720133 is located in an embedded ROM.