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UPB409-2 - 2K x 8-BIT BIPOLA TTL PROM

Download the UPB409-2 datasheet PDF. This datasheet also covers the UPB429 variant, as both devices belong to the same 2k x 8-bit bipola ttl prom family and are provided as variant models within a single manufacturer datasheet.

Key Features

  • 2048 WORDS x 8 BITS Organization (Fully Decoded).
  • TT L Interface.
  • Fast Read Access Time :50 ns MAX.
  • Medium Power Consumption :500 mW TyP.
  • Three Chip Enable Inputs for Memory Expansion.
  • Open-Collector Outputs (JlPB409).
  • Three-State Outputs (JlPB429).
  • Ceramic 24-Lead Dual In-Line Package (JlPB409D, JlPB429D).
  • Plastic.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (UPB429_NEC.pdf) that lists specifications for multiple related part numbers.

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Other Datasheets by NEC (now Renesas Electronics)

Part Number Description
UPB409-1 2K x 8-BIT BIPOLA TTL PROM
UPB409 2K x 8-BIT BIPOLA TTL PROM
UPB406 4K-BIT BIPOLAR TTL PROGRAMMABLE READ ONLY MEMORY
UPB406-1 4K-BIT BIPOLAR TTL PROGRAMMABLE READ ONLY MEMORY
UPB406-2 4K-BIT BIPOLAR TTL PROGRAMMABLE READ ONLY MEMORY

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
NEe Microcomputers, Inc. NEe p.PB409 J'!PB429 ",PB409-1 }LPB429-1 p.PB409-2 ILPB429-2 2048 WORD BY 8 BIT BIPOLAR TTL PROGRAMMABLE READ ONLY MEMORY DESC RIPT ION The JlPB409 and JlPB429 are high-speed, electrically programmable, fully-decoded 16384 bit TTL read only memories. On-chip address decoding, three chip enable inputs and open-collector/three-state outputs allow easy expansion of memory capacity. The JlPB409 and JlPB429 are fabricated with logic level zero (low); logic level one (high) can be electrically programmed into the selected bit locations. The . same address inputs are used for both programming and reading.