UPD16448A
FEATURES
- Can be driven on 5 V (Dynamic range: 4.3 V, VDD2 = 5.0 V)
- 240-output
- fmax. = 18 MHz (VDD1 = 3.0 V)
- Simultaneous/successive sampling selectable according to pixel array Simultaneous sampling: vertical stripe Successive sampling:
- Two sample and hold circuits
- Low output deviation between pins (± 20 m V MAX.)
- Stripe, delta, and mosaic pixel arrays supported by internal multiplexer circuit
- Left and right shift selected by R/L pin
- Single-side mounting possible delta array, mosaic array
ORDERING INFORMATION
Part Number
µPD16448AN-×××
Package
TCP (TAB package)
Remark The dimensions of TCP are custom-made. Please consult NEC for details.
The information in this document is subject to change without notice. Document No. S11712EJ3V0DS00 (3rd edition) Date Published August 1998 NS CP(K) Printed in Japan The mark 5 shows major revised points.
©
µPD16448A
BLOCK DIAGRAM
CLI1 to 3 R/L STHR 240-bit shift register STHL 3
INH 240-bit level shifter RESET
VDD1 +3.3...
