UPD16448A Overview
Symbol C1 to C3 H1 to H240 STHR STHL CLI1 CLI2 CLI3 INH RESET Name Video signal input Video signal output Cascade I/O Input R, G, and B video signals. Video signal output pins. Output sampled and held video signals during horizontal period.
UPD16448A Key Features
- Can be driven on 5 V (Dynamic range: 4.3 V, VDD2 = 5.0 V)
- 240-output
- fmax. = 18 MHz (VDD1 = 3.0 V)
- Simultaneous/successive sampling selectable according to pixel array Simultaneous sampling: vertical stripe Successive s
- Two sample and hold circuits
- Low output deviation between pins (± 20 mV MAX.)
- Stripe, delta, and mosaic pixel arrays supported by internal multiplexer circuit
- Left and right shift selected by R/L pin
- Single-side mounting possible delta array, mosaic array
- H5 H4 H3 H2 H1