NEC UPD16662
240 OUTPUT LCD COLUMN SEGMENT DRIVER
FEATURES
● Display RAM incorporated: 240 x 160 x 2 bits● Logic voltage: 3.0V to 3.6V
● Duty: 1/160
● Output count: 240 outputs
● Capable of gray scale display: 4 gray scales (can be selected from 25 levels of the gray scale pallet)
● Memory management: packed pixel system
● 8/16-bit data base Ordering Information Part number Package TCP(TAB) Standard TCP (OLB: 0.2 mm pitch; folding) µPD16662N -×××
● µPD16662N - 051 The TCP’s external shape is custom-ordered. Therefore, if you have a shape in mind, please contact an NEC salesperson. The information in this document is subject to change without notice. Document No. S12738EJ3V0DS00 (3rd edition) Date Published November 1998 NS CP (K) Printed in Japan The mark
● shows major revised points. © 1998 µPD16662 Pin name Classification CPU I/F Voltage 3.3 V Pin Name D0 to D15 A0 to A16 /CS /OE /WE /UBE RDY Control signals 3.3 V PL0 PL1 DIR Note I/O I/O I I I I I O I I I Data bus 16 Address bus 17 Chip select Read signal Write signal High byte enable Function Ready signal to CPU (Ready state at H) Specifies the LSI allocation locations (No.