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UPD411A-1 - 4096-BIT DYNAMIC RAMS

Download the UPD411A-1 datasheet PDF. This datasheet also covers the UPD411A variant, as both devices belong to the same 4096-bit dynamic rams family and are provided as variant models within a single manufacturer datasheet.

Key Features

  • Low Standby Power.
  • 4096 words x 1 bit Organization.
  • A single low.
  • capacitance high level clock input with solid ±1 volt margins.
  • Inactive Power 0.7 mW (Typ. ).
  • Power Supply +12, +5, -5V.
  • Easy System Interface.
  • TTL Compatible (Except CE).
  • Address Registers on th.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (UPD411A-NEC.pdf) that lists specifications for multiple related part numbers.

📁 Similar Datasheet

Part Number Description Manufacturer
UPD41256 262144 Dynamic NMOS RAM NEC Electronics
UPD41257 262144 Dynamic NMOS RAM NEC Electronics
UPD41264 Dual Port Graphics Buffer NEC Electronics
UPD41264C Dual Port Graphics Buffer NEC Electronics
UPD41416 16K x 4-Bit DRAM NEC Electronics

Other Datasheets by NEC (now Renesas Electronics)

Part Number Description
UPD411A-2 4096-BIT DYNAMIC RAMS
UPD411A 4096-BIT DYNAMIC RAMS
UPD411 FULLY DECODED RANDOM ACCESS MEMORY
UPD411-1 FULLY DECODED RANDOM ACCESS MEMORY
UPD411-2 FULLY DECODED RANDOM ACCESS MEMORY

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
NEe Microcomputers, Inc. NEe Jl.PD411A Jl.PD411A-1 Jl.PD411A-2 DESCR IPTION 4096 BIT DYNAMIC RAMS The ,uPD411A Famify consists of four 4096 words by 1 bit dynamic N-channel MOS RAMs. They are designed for memory applications where very low cost and large bit storage are important design objectives. The ,uPD411 A Family is designed using dynamic circuitry which reduces the standby power dissipation. Reading information from the memory is non·destructive. Refreshing is easily II accomplished by performing one read cycle on each of the 64 row addresses. Each row address must be refreshed every two milliseconds. The memory is refreshed whether Chip Select is a logic high or a logic low.