UPD44324084 - 36M-BIT DDRII SRAM

The µPD44324084 is a 4,194,304-word by 8-bit, the µPD44324094 is a 4,194,304-word by 9-bit, the µPD44324184 is a 2,097,152-word by 18-bit and the µPD44324364 is a 1,048,576-word by 36-bit synchronous double data rate static RAM fabricated with advanced CMOS technology using full CMOS six-transistor

• 1.8 ± 0.1 V power supply and HSTL I/O.
• DLL circuitry for wide output data valid window and future frequency scaling.
• Pipelined double data rate operation.
• Common data input/output bus.
• Four-tick burst for reduced address frequency.
• Two input clocks (K and /K) for precise DDR timing at clock rising edges only.
• Two output clocks (C and /C) for precise flight time and clock skew matching-clock and data delivered together to receiving d.