UPD44324185
Description
The µPD44324085 is a 4,194,304-word by 8-bit, the µPD44324095 is a 4,194,304-word by 9-bit, the µPD44324185 is a 2,097,152-word by 18-bit and the µPD44324365 is a 1,048,576-word by 36-bit synchronous double data rate static RAM fabricated with advanced CMOS technology using full CMOS six-transistor memory cell.
Key Features
- 1.8 ± 0.1 V power supply and HSTL I/O
- DLL circuitry for wide output data valid window and future frequency scaling
- Separate independent read and write data ports
- DDR read or write operation initiated each cycle
- Pipelined double data rate operation
- Separate data input/output bus
- Two-tick burst for low DDR transaction size
- Two input clocks (K and /K) for precise DDR timing at clock rising edges only
- Two output clocks (C and /C) for precise flight time and clock skew matching-clock and data delivered together to receiving device
- Internally self-timed write control
