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UPD44325092 - 36M-BIT QDRII SRAM

Download the UPD44325092 datasheet PDF. This datasheet also covers the UPD44325082 variant, as both devices belong to the same 36m-bit qdrii sram family and are provided as variant models within a single manufacturer datasheet.

General Description

The µPD44325082 is a 4,194,304-word by 8-bit, the µPD44325092 is a 4,194,304-word by 9-bit, the µPD44325182 is a 2,097,152-word by 18-bit and the µPD44325362 is a 1,048,576-word by 36-bit synchronous quad data rate static RAM fabricated with advanced CMOS technology using full CMOS six-transistor me

Key Features

  • 1.8 ± 0.1 V power supply and HSTL I/O.
  • DLL circuitry for wide output data valid window and future frequency scaling.
  • Separate independent read and write data ports with concurrent transactions.
  • 100% bus utilization DDR READ and WRITE operation.
  • Two-tick burst for low DDR transaction size.
  • Two input clocks (K and /K) for precise DDR timing at clock rising edges only.
  • Two output clocks (C and /C) for precise flight time and clock skew.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (UPD44325082_NEC.pdf) that lists specifications for multiple related part numbers.

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
www.DataSheet4U.com PRELIMINARY DATA SHEET MOS INTEGRATED CIRCUIT µPD44325082, 44325092, 44325182, 44325362 36M-BIT QDRTMII SRAM 2-WORD BURST OPERATION Description The µPD44325082 is a 4,194,304-word by 8-bit, the µPD44325092 is a 4,194,304-word by 9-bit, the µPD44325182 is a 2,097,152-word by 18-bit and the µPD44325362 is a 1,048,576-word by 36-bit synchronous quad data rate static RAM fabricated with advanced CMOS technology using full CMOS six-transistor memory cell. The µPD44325082, µPD44325092, µPD44325182 and µPD44325362 integrate unique synchronous peripheral circuitry and a burst counter. All input registers controlled by an input clock pair (K and /K) are latched on the positive edge of K and /K.