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UPD4564323 - 64M-bit Synchronous DRAM 4-bank/ LVTTL

General Description

The µPD4564323 is a high-speed 67,108,864-bit synchronous dynamic random-access memory, organized as 524,288 words × 32 bits × 4 banks.

The synchronous DRAMs achieved high-speed data transfer using the pipeline architecture.

Key Features

  • Fully Synchronous Dynamic RAM, with all signals referenced to a positive clock edge.
  • Pulsed interface.
  • Possible to assert random column address in every cycle.
  • Quad internal banks controlled by BA0 and BA1 (Bank Select).
  • ×32 organization.
  • Byte control by DQM0, DQM1, DQM2 and DQM3.
  • Programmable Wrap sequence (Sequential / Interleave).
  • Programmable burst length (1, 2, 4, 8 and full page).
  • Programmable /CAS latency (2.

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Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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DATA SHEET MOS INTEGRATED CIRCUIT µ PD4564323 64M-bit Synchronous DRAM 4-bank, LVTTL for Rev. E Description The µPD4564323 is a high-speed 67,108,864-bit synchronous dynamic random-access memory, organized as 524,288 words × 32 bits × 4 banks. The synchronous DRAMs achieved high-speed data transfer using the pipeline architecture. All inputs and outputs are synchronized with the positive edge of the clock. The synchronous DRAMs are compatible with Low Voltage TTL (LVTTL). These products are packaged in 86-pin TSOP (II).