Datasheet4U Logo Datasheet4U.com

UPD4564841 - 64M-bit Synchronous DRAM

Download the UPD4564841 datasheet PDF. This datasheet also covers the UPD4564441 variant, as both devices belong to the same 64m-bit synchronous dram family and are provided as variant models within a single manufacturer datasheet.

General Description

The µPD4564441, 4564841, 4564163 are high-speed 67,108,864-bit synchronous dynamic random-access memories, organized as 4,194,304 × 4 × 4, 2,097,152 × 8 × 4, 1,048,576 ×16 × 4 (word × bit × bank), respectively.

The synchronous DRAMs achieved high-speed data transfer using the pipeline architecture.

Key Features

  • Fully Synchronous Dynamic RAM, with all signals referenced to a positive clock edge.
  • Pulsed interface.
  • Possible to assert random column address in every cycle.
  • Quad internal banks controlled by A12 and A13 (Bank Select).
  • Byte control (×16) by LDQM and UDQM.
  • Programmable Wrap sequence (Sequential / Interleave).
  • Programmable burst length (1, 2, 4, 8 and full page).
  • Programmable /CAS latency (2 and 3).
  • Automatic prech.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (UPD4564441-NEC.pdf) that lists specifications for multiple related part numbers.

📁 Similar Datasheet

Part Number Description Manufacturer
UPD4564841 (UPD4564841/441/163) 64M-bit SDRAM Elpida Memory
UPD4564163 (UPD4564841/441/163) 64M-bit SDRAM Elpida Memory
UPD4564441 (UPD4564841/441/163) 64M-bit SDRAM Elpida Memory
UPD4503B Hex 2 State Buffer ETC
UPD4516161D 16M Bit Synchronous DRAM Elpida

Other Datasheets by NEC (now Renesas Electronics)

Part Number Description
UPD4564163 64M-bit Synchronous DRAM
UPD4564163G5 64M Bit SDRAM
UPD4564323 64M-bit Synchronous DRAM 4-bank/ LVTTL
UPD4564441 64M-bit Synchronous DRAM
UPD45128163 128M-bit Synchronous DRAM 4-bank/ LVTTL

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
DATA SHEET MOS INTEGRATED CIRCUIT µPD4564441, 4564841, 4564163 64M-bit Synchronous DRAM 4-bank, LVTTL Description The µPD4564441, 4564841, 4564163 are high-speed 67,108,864-bit synchronous dynamic random-access memories, organized as 4,194,304 × 4 × 4, 2,097,152 × 8 × 4, 1,048,576 ×16 × 4 (word × bit × bank), respectively. The synchronous DRAMs achieved high-speed data transfer using the pipeline architecture. All inputs and outputs are synchronized with the positive edge of the clock. The synchronous DRAMs are compatible with Low Voltage TTL (LVTTL). These products are packaged in 54-pin TSOP (II).