UPD70320 Datasheet | NEC

- - - - - - - Internal 16-bit architecture and external 8-bit data bus patible with µPD70108/ 70116 (in native mode) on software level (some instructions added) Minimum instruction cycle : 400 ns/5 MHz (µPD70320) 250 ns/8 MHz (µPD70320-8) On-chip RAM : 256 words × 8 bits Input port (port T) with parator : 8 bits I/O lines (input port : 4 bits, input/output port : 20 bits) Serial interface (internal dedicated baud rate generator) : 2 channels Asynchronous mode and I/O interface mode Interrupt controller - Programmable priority (8 levels) - Vectored interrupt function - Register bank switching function - Macro service function - - - - - - - DRAM and pseudo SRAM refreshing functions DMA controller : 2 channels 16-bit timer : 2 channels Time base counter On-chip clock generator Programmable wait function Standby function (STOP/HALT) The information in this document is subject to change without notice. Document No. U10090EJ8V0DS00 (8th edition) Date Published November 1997 N Printed in Japan The mark shows major revised points. © 1996 1995 µPD70320 ORDERING INFORMATION Part Number Package 84-pin plastic QFJ (1150 × 1150 mils) 84-pin plastic QFJ (1150 × 1150 mils) 94-pin plastic QFP (20 × 20 mm) 94-pin plastic QFP (20 × 20 mm) Max. Operating Frequency (MHz) 5 8 5 8 µPD70320L µPD70320L-8 µPD70320GJ-5BG µPD70320GJ-8-5BG Remark The plastic QFJ is a new name of the PLCC. µPD70320 PIN CONFIGURATION (Top View) 84-Pin Plastic QFJ (1150 × 1150 mils) µPD70320L µPD70320L-8 REFRQ RESET IOSTB MREQ MSTB...