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UPD98405 - 155M ATM INTEGRATED SAR CONTROLLER

Datasheet Summary

Description

ATM cells.

It has a PCI bus interface, a SONET/SDH 155-Mbps framer, and a clock recovery circuit and supports an ABR function in hardware.

Features

  • Conforms to ATM Forum.
  • Host bus interface supporting PCI bus/generic bus. - PCI interface (5/3.3 V, 32/64 bits, 33 MHz): Conforms to PCI Specification 2.1 - Generic bus interface (5/3.3 V, 32 bits, 33 MHz).
  • AAL-5 SAR sublayer, ATM layer, and TC sublayer functions.
  • Hardware support of AAL-5 processing.
  • Software support of non-AAL-5 traffic.
  • SONET STS-3c/SDH STM-1 155-Mbps framer function.
  • Clock recovery/clock synthesizer function.

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Datasheet preview – UPD98405

Datasheet Details

Part number UPD98405
Manufacturer NEC
File Size 333.71 KB
Description 155M ATM INTEGRATED SAR CONTROLLER
Datasheet download datasheet UPD98405 Datasheet
Additional preview pages of the UPD98405 datasheet.

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Full PDF Text Transcription

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DATA SHEET MOS INTEGRATED CIRCUIT µPD98405 155M ATM INTEGRATED SAR CONTROLLER DESCRIPTION The µPD98405 (NEASCOT-S20TM) is a high-performance SAR chip that performs segmentation and reassembly of ATM cells. It has a PCI bus interface, a SONET/SDH 155-Mbps framer, and a clock recovery circuit and supports an ABR function in hardware. The µPD98405 conforms to ATM Forum and has the functions of the AAL-5 SAR sublayer, ATM layer, and TC sublayer. FEATURES • Conforms to ATM Forum. • Host bus interface supporting PCI bus/generic bus. - PCI interface (5/3.3 V, 32/64 bits, 33 MHz): Conforms to PCI Specification 2.1 - Generic bus interface (5/3.
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