UPD98405 Description
The µPD98405 (NEASCOT-S20TM) is a high-performance SAR chip that performs segmentation and reassembly of ATM cells. It has a PCI bus interface, a SONET/SDH 155-Mbps framer, and a clock recovery circuit and supports an ABR function in hardware. The µPD98405 conforms to ATM Forum and has the functions of the AAL-5 SAR sublayer, ATM layer, and TC sublayer.
UPD98405 Key Features
- Conforms to ATM Forum
- Host bus interface supporting PCI bus/generic bus
- Generic bus interface (5/3.3 V, 32 bits, 33 MHz)
- AAL-5 SAR sublayer, ATM layer, and TC sublayer functions
- Hardware support of AAL-5 processing
- Software support of non-AAL-5 traffic
- SONET STS-3c/SDH STM-1 155-Mbps framer function
- Clock recovery/clock synthesizer function
- Supports up to 32 K virtual channels (VCs)
- Sixteen traffic shapers for VBR for transmission scheduling