S7A803630M Overview
The S7A803630M and S7A801830M are 9,437,184-bit Synchronous Static Random Access Memory designed for high performance. It is organized as 256K(512K) words of 36(18) bits and integrates address and control registers, a 2-bit burst address counter and added some new functions for high performance applications; Write cycles are internally selftimed and synchronous.
S7A803630M Key Features
- Synchronous Operation
- 2 Stage Pipelined operation with 4 Burst
- On-Chip Address Counter
- Self-Timed Write Cycle
- On-Chip Address and Control Registers
- Byte Writable Function
- Global Write Enable Controls a full bus-width write
- Power Down State via ZZ Signal
- LBO Pin allows a choice of either a interleaved burst or a lin
- Three Chip Enables for simple depth expansion with No Data