NETSOL S7B161835M
The S7B163635M and S7B161835M are 18,874,368-bit Synchronous Static Random Access Memory designed for high performance. It is organized as 512K(1M) words of 36(18) bits and integrates address and control registers, a 2-bit burst address counter and added some new functions for high performance applications; GW, BW, LBO, ZZ. The S7B163635M and S7B161835M are fabricated using high performance CMOS technology and is available in a 100pin TQFP package.| Part No. | S7B161835M |
|---|---|
| Datasheet | S7B161835M Download |
| Manufacturer | NETSOL |
| Description | 512Kx36 & 1Mx18 Flow-Through SRAM |
| Buy | Stock & Price |
FEATURES
● VDD = 2.5V(2.3V ~ 2.7V) or 3.3V(3.1V ~ 3.5V) Power Supply● VDDQ = 2.3V~2.7V I/O Power Supply (VDD=2.5V) or 2.3V~3.5V I/O Power Supply (VDD=3.3V)
● Synchronous Operation
● Self-Timed Write Cycle
● On-Chip Address Counter and Control Registers
● Byte Writable Function
● Global Write Enable Controls a full bus-width write
● Power Down State via ZZ Signal
● LBO Pin allows a choice of either a interleaved burst or a lin- ear burst
● Three Chip Enables for simple depth expansion with No Data Contention only for TQFP
● Asynchronous Output Enable Control
● ADSP, ADSC, ADV Burst Control Pins
● TTL-Level Three-State Output
● Operating in commeical and industrial temperature range
● 100-TQFP-1420A (Lead free package)
GENERAL DESCRIPTION
Write cycles are internally self-timed and synchronous. Full bus-width write is done by GW, and each byte write is performed by the combination of WEx and BW when GW is high. And with CS1 high, ADSP is blocked to control signals. Burst cycle can be initiated with either the address status processor(ADSP) or address status cache controller(ADSC) inputs.
