NETSOL S7I163682M
The S7I163682M and S7I161882M are 18,874,368-bits DDR Common I/O Synchronous Pipelined Burst SRAMs. They are organized as 524,288 words by 36bits for S7I163682M and 1,048,576 words by 18 bits for S7I161882M. The S7I163682M and S7I161882M are implemented with Netsol's high performance 6T CMOS technology and is available in 165pin FBGA packages.| Part No. | S7I163682M |
|---|---|
| Datasheet | S7I163682M Download |
| Manufacturer | NETSOL |
| Description | 512Kx36 & 1Mx18 DDRII CIO BL2 SRAM |
| Buy | Stock & Price |
FEATURES
●1.8V+0.1V/-0.1V Power Supply.●DLL circuitry for wide output data valid window and future fre- quency scaling.
● I/O Supply Voltage 1.5V+0.1V/-0.1V for 1.5V I/O, 1.8V+0.1V/-0.1V for 1.8V I/O
●Pipelined, double-data rate operation.
● Common data input/output bus.
● HSTL I/O
● Full data coherency, providing most current data.
● Synchronous pipeline read with self timed late write.
● Registered address, control and data input/output.
● DDR (Double Data Rate) Interface on read and write ports.
● Fixed 2-bit burst for both read and write operation.
● Clock-stop supports to reduce current.
●Two input clocks (K and K) for accurate DDR timing at clock rising edges only.
●Two input clocks for output data (C and C) to minimize clock-skew and flight-time mismatches.
●Two echo clocks (CQ and CQ) to enhance output data traceability.
●Single address bus.
●Byte write (x18, x36) function.
● Simple depth expansion with no data contention.
●Programmable output impedance.
● JTAG 1149.1 compatible test access port.
