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S7I163682M - 512Kx36 & 1Mx18 DDRII CIO BL2 SRAM

Datasheet Summary

Description

The S7I163682M and S7I161882M are 18,874,368-bits DDR Common I/O Synchronous Pipelined Burst SRAMs.

They are organized as 524,288 words by 36bits for S7I163682M and 1,048,576 words by 18 bits for S7I161882M.

Address, data inputs, and all control signals are synchronized to the input clock (K or K).

Features

  • 1.8V+0.1V/-0.1V Power Supply.
  • DLL circuitry for wide output data valid window and future fre- quency scaling.
  • I/O Supply Voltage 1.5V+0.1V/-0.1V for 1.5V I/O, 1.8V+0.1V/-0.1V for 1.8V I/O.
  • Pipelined, double-data rate operation.
  • Common data input/output bus.
  • HSTL I/O.
  • Full data coherency, providing most current data.
  • Synchronous pipeline read with self timed late write.
  • Registered address, control and data in.

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Datasheet Details

Part number S7I163682M
Manufacturer NETSOL
File Size 364.33 KB
Description 512Kx36 & 1Mx18 DDRII CIO BL2 SRAM
Datasheet download datasheet S7I163682M Datasheet
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SS77I1I16633668822MM SS77I1I16611888822MM 512Kx36 & 1Mx18 DDRII CIO BL2 SRAM 18Mb DDRII CIO BL2 SRAM Specification 165FBGA with Pb & Pb Free (ROHS Compliant) NETSOL RESERVES THE RIGHT TO CHANGE PRODUCTS, INFORMATION AND SPECIFICATIONS WITHOUT NOTICE. Products and specifications discussed herein are for reference purposes only. All information discussed herein is provided on an "AS IS" basis, without warranties of any kind. This document and all information discussed herein remain the sole and exclusive property of NETSOL. No license of any patent, copyright, mask work, trademark or any other intellectual property right is granted by one party to the other party under this document, by implication, estoppel or otherwise.
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