S7I321882M Datasheet PDF - NETSOL 1Mx36 & 2Mx18 DDRII CIO BL2 SRAM Specs

S7I321882M - 1Mx36 & 2Mx18 DDRII CIO BL2 SRAM

This page provides the datasheet information for the S7I321882M, a member of the S7I323682M 1Mx36 & 2Mx18 DDRII CIO BL2 SRAM family.

Datasheet Summary

Description

The S7I323682M and S7I321882M are 37,748,736-bits DDR Common I/O Synchronous Pipelined Burst SRAMs.

They are organized as 1,048,576 words by 36bits for S7I323682M and 2,097,152 words by 18 bits for S7I321882M.

Features

1.8V+0.1V/-0.1V Power Supply.
DLL circuitry for wide output data valid window and future fre- quency scaling.
I/O Supply Voltage 1.5V+0.1V/-0.1V for 1.5V I/O, 1.8V+0.1V/-0.1V for 1.8V I/O.
Pipelined, double-data rate operation.
Common data input/output bus.
HSTL I/O.
Full data coherency, providing most current data.
Synchronous pipeline read with self timed late write.
Registered address, control and data in.

Datasheet Details

Part number	S7I321882M
Manufacturer	NETSOL
File Size	364.88 KB
Description	1Mx36 & 2Mx18 DDRII CIO BL2 SRAM
Datasheet	S7I321882M Datasheet
Additional preview pages of the S7I321882M datasheet.

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SSSS7777II33II3322221331866888882222MMMM 11MMxx3366 && 22MMxx1188 DDDDRRIIII CCIIOO BBLL22 SSRRAAMM 36Mb DDRII CIO BL2 SRAM Specification 165FBGA with Pb & Pb Free (ROHS Compliant) NETSOL RESERVES THE RIGHT TO CHANGE PRODUCTS, INFORMATION AND SPECIFICATIONS WITHOUT NOTICE. Products and specifications discussed herein are for reference purposes only. All information discussed herein is provided on an "AS IS" basis, without warranties of any kind. This document and all information discussed herein remain the sole and exclusive property of NETSOL. No license of any patent, copyright, mask work, trademark or any other intellectual property right is granted by one party to the other party under this document, by implication, estoppel or otherwise.

Published: Oct 13, 2018 |

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