S7K1636U2M Datasheet PDF - NETSOL 512Kx36 & 1Mx18 DDRII+ CIO BL2 SRAM Specs

S7K1636U2M - 512Kx36 & 1Mx18 DDRII+ CIO BL2 SRAM

Datasheet Summary

Description

The S7K1636U2M and S7K1618U2M are 18,874,368-bits DDR Common I/O Synchronous Pipelined Burst SRAMs.

They are organized as 524,288 words by 36bits for S7K1636U2M and 1,048,576 words by 18 bits for S7K1618U2M.

Address, data inputs, and all control signals are synchronized to the input clock (K or K).

Features

Key Parameters.
1.8V+0.1V/-0.1V Power Supply.
DLL circuitry for wide output data valid window and future fre- quency scaling.
I/O Supply Voltage 1.5V+0.1V/-0.1V for 1.5V I/O, 1.8V+0.1V/ Part Number Org. Freq. (MHz) Cycle Access Time Time RoHS (ns) (ns) -0.1V for 1.8V I/O.
Pipelined, double-data rate operation.
Common data input/output bus.
HSTL I/O.
Full data coherency, providing most current data.
Synchronous p.

Datasheet Details

Part number	S7K1636U2M
Manufacturer	NETSOL
File Size	360.53 KB
Description	512Kx36 & 1Mx18 DDRII+ CIO BL2 SRAM
Datasheet	S7K1636U2M Datasheet
Additional preview pages of the S7K1636U2M datasheet.

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SSSS7777KKKK1111666613318668UUUU2222MMMM 551122KKxx3366&&11MMxx1188DDDDRRIIII++CCIIOOBBLL22SSRRAAMM 18Mb DDRII+ CIO BL2 SRAM Specification (2.5 Clock Read Latency) 165FBGA with Pb & Pb Free (ROHS Compliant) NETSOL RESERVES THE RIGHT TO CHANGE PRODUCTS, INFORMATION AND SPECIFICATIONS WITHOUT NOTICE. Products and specifications discussed herein are for reference purposes only. All information discussed herein is provided on an "AS IS" basis, without warranties of any kind. This document and all information discussed herein remain the sole and exclusive property of NETSOL. No license of any patent, copyright, mask work, trademark or any other intellectual property right is granted by one party to the other party under this document, by implication, estoppel or otherwise.

Published: Oct 13, 2018 |

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