S7K6436U2M Description
The S7K6436U2M and S7K6418U2M are 75,497,472-bits DDR mon I/O.
S7K6436U2M Key Features
- 1.8V+0.1V/-0.1V Power Supply. -DLL circuitry for wide output data valid window and future fre
- mon data input/output bus
- HSTL I/O
- Full data coherency, providing most current data
- Synchronous pipeline read with self timed late write
- Read latency : 2.5 clock cycles
- Registered address, control and data input/output
- DDR (Double Data Rate) Interface on read and write ports
- Fixed 2-bit burst for both read and write operation
- Clock-stop supports to reduce current. -Two input clocks (K and K) for accurate DDR timing at clock