NETSOL S7L1636U2M
The S7L1636U2M and S7L1618U2M are 18,874,368-bits DDR Common I/O Synchronous Pipelined Burst SRAMs. They are organized as 524,288 words by 36bits for S7L1636U2M and 1,048,576 words by 18 bits for S7L1618U2M. The S7L1636U2M and S7L1618U2M support On Die Termination (ODT) for data input, input clock (K, K) and BWx.| Part No. | S7L1636U2M |
|---|---|
| Datasheet | S7L1636U2M Download |
| Manufacturer | NETSOL |
| Description | 512Kx36 & 1Mx18 DDRII+ CIO BL2 SRAM w/ ODT |
| Buy | Stock & Price |
FEATURES
KEY PARAMETERS
●1.8V+0.1V/-0.1V Power Supply.●DLL circuitry for wide output data valid window and future fre- quency scaling.
● I/O Supply Voltage 1.5V+0.1V/-0.1V for 1.5V I/O, 1.8V+0.1V/ Part Number Org. Freq. (MHz) Cycle Access Time Time RoHS (ns) (ns) -0.1V for 1.8V I/O
●Pipelined, double-data rate operation.
● Common data input/output bus.
● HSTL I/O
● Full data coherency, providing most current data.
● Synchronous pipeline read with self timed late write. S7L1636U2M-E(F)C(I)55 550 1.8 0.45 S7L1636U2M-E(F)C(I)50 x36 500 2.0 0.45 S7L1636U2M-E(F)C(I)45 450 2.2 0.45 S7L1636U2M-E(F)C(I)40 400 2.5 0.45
● Read latency : 2.5 clock cycles
● Registered address, control and data input/output.
● DDR (Double Data Rate) Interface on read and write ports. S7L1618U2M-E(F)C(I)55 550 1.8 0.45 S7L1618U2M-E(F)C(I)50 x18 500 2.0 0.45
● Fixed 2-bit burst for both read and write operation. S7L1618U2M-E(F)C(I)45 450 2.2 0.45
● Clock-stop supports to reduce current.
●Two input...
