NETSOL S7L6418U2M
The S7L6436U2M and S7L6418U2M are 75,497,472-bits DDR Common I/O Synchronous Pipelined Burst SRAMs. They are organized as 2.097,152 words by 36bits for S7L6436U2M and 4,194,304 words by 18 bits for S7L6418U2M. The S7L6436U2M and S7L6418U2M are implemented with Netsol's high performance 6T CMOS technology and is available in 165pin FBGA packages.| Part No. | S7L6418U2M |
|---|---|
| Datasheet | S7L6418U2M Download |
| Manufacturer | NETSOL |
| Description | 2Mx36 & 4Mx18 DDRII+ CIO BL2 SRAM w/ ODT |
| Buy | Stock & Price |
FEATURES
KEY PARAMETERS
● 1.8V+0.1V/-0.1V Power Supply.● DLL circuitry for wide output data valid window and future fre- quency scaling.
● I/O Supply Voltage 1.5V+0.1V/-0.1V for 1.5V I/O, 1.8V+0.1V/-0.1V for 1.8V I/O.
● Pipelined, double-data rate operation.
● Common data input/output bus.
● HSTL I/O
● Full data coherency, providing most current data.
● Synchronous pipeline read with self timed late write.
● Read latency : 2.5 clock cycles
● Registered address, control and data input/output.
● DDR (Double Data Rate) Interface on read and write ports.
● Fixed 2-bit burst for both read and write operation.
● Clock-stop supports to reduce current.
● Two input clocks (K and K) for accurate DDR timing at clock rising edges only.
● Two echo clocks (CQ and CQ) to enhance output data traceability.
● Data Valid pin(QVLD) supported
● On die termination (ODT) supported for data input, K, K and BWx.
● Single address bus.
● Byte write (x18, x36) function.
● Simple depth expansion with no data contention.
