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S7N321831M Datasheet PDF

NETSOL S7N321831M

The S7N323631M and S7N321831M are 37,748,736-bits Synchronous Static SRAMs. The NTSRAM, or Non-Turnaround Static Random Access Memory utilizes all the bandwidth in any combination of operating cycles. The S7N323631M and S7N321831M are implemented with high performance CMOS technology and is available in 100pin TQFP package and 165FBGA package.
Part No. S7N321831M
Datasheet S7N321831M Download
Manufacturer NETSOL
Description 1Mx36 & 2Mx18 NTSRAM Sync-Pipelined Burst
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S7N321831M datasheet page 1 preview

FEATURES

● Fully registered inputs and outputs for pipelined operation
● VDD = 1.8V (1.7V ~ 2.0V) or 2.5V (2.3V ~ 2.7V) or 3.3V (3.1V ~ 3.5V) Power Supply
● VDDQ = 1.7V ~ 2.0V I/O Power Supply (VDD=1.8V) or 2.3V ~ 2.7V I/O Power Supply (VDD=2.5V) or 2.3V ~ 3.5V I/O Power Supply (VDD=3.3V)
● Byte Writable Function
● Enable clock and suspend operation
● Single Read/Write control pin
● Asynchronous output enable control
● Self-timed Write control
● Three Chip Enable for simple depth expansion with no data contention
● An interleaved burst or a linear burst mode
● Power Down mode
● Operating in commeical and industrial temperature range
● 100-TQFP-1420A (Lead free package)
● 165FBGA(11x15 ball array) with body size of 13mmx15mm. (Lead free package)

GENERAL DESCRIPTION

Address, data inputs, and all control signals except output enable and linear burst order are synchronized to input clock. Burst order control must be tied "High or Low". Asynchronous inputs include the sleep mode enable(ZZ). Output Enable controls the outputs at any given time.
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